Embodiments of the present disclosure relate generally to an interposer for inspecting the reliability of a semiconductor chip, and, more particularly, to an inspection interposer for testing a high-performance semiconductor chip according to an active and/or passive method.
With the rapid development of the semiconductor memory industry, semiconductor devices have been developed to implement low-priced products having lighter weights, smaller sizes, and higher degree of integration. In recent times, many developers and companies are conducting intensive research into three dimensional (3D) integrated circuits, such as stacked chip packages. Generally, a 3D integrated circuit includes an interposer for interconnect the stacked semiconductor chips. The interposer typically includes an insulation substrate and a plurality of conductive patterns embedded in the insulation substrate. The conductive patterns are coupled electrically to the stacked semiconductor chips.
In recent times, high-performance mobile DRAMs such as Wide IO2 (WIO2) have been developed. Since each high-performance mobile DRAM includes a large number of bumps, it is nearly impossible to manufacture a package for inspecting WIO2 reliability only using the WIO2. Furthermore, since the WIO2 includes a micro bump, it is difficult to inspect reliability of the micro bump when the package is manufactured using wire bonding or the like.
The present invention overcomes these issues associated with the prior art by employing a new interposer disposed between a substrate (PCB) and a high-performance semiconductor chip such as a WIO2 for inspecting the reliability of the high-performance semiconductor chip.